The Definitive Guide to the ARM Cortex-M3.

Front Cover -- The Definitive Guide to the ARM Cortex-M3 -- Copyright Page -- Table of Contents -- Foreword -- Preface -- Acknowledgments -- Terms and Abbreviations -- Conventions -- References -- Chapter 1 - Introduction -- What Is the ARM Cortex-M3 Processor? -- Background of ARM and ARM Architecture -- A Brief History -- Architecture Versions -- Processor Naming -- Instruction Set Development -- The Thumb-2 Instruction Set Architecture (ISA) -- Cortex-M3 Processor Applications -- Organization of This Book -- Further Readings -- Chapter 2 - Overview of the Cortex-M3 -- Fundamentals -- Registers -- R0 to R12: General-Purpose Registers -- R13: Stack Pointers -- R14: The Link Register -- R15: The Program Counter -- Special Registers -- Operation Modes -- The Built-In Nested Vectored Interrupt Controller -- Nested Interrupt Support -- Vectored Interrupt Support -- Dynamic Priority Changes Support -- Reduction of Interrupt Latency -- Interrupt Masking -- The Memory Map -- The Bus Interface -- The Memory Protection Unit -- The Instruction Set -- Interrupts and Exceptions -- Debugging Support -- Characteristics Summary -- High Performance -- Advanced Interrupt-Handling Features -- Low Power Consumption -- System Features -- Debug Supports -- Chapter 3 - Cortex-M3 Basics -- Registers -- General-Purpose Registers R0-R7 -- General-Purpose Registers R8-R12 -- Stack Pointer R13 -- Link Register R14 -- Program Counter R15 -- Special Registers -- Program Status Registers (PSRs) -- PRIMASK, FAULTMASK, and BASEPRI Registers -- The Control Register -- Operation Mode -- Exceptions and Interrupts -- Vector Tables -- Stack Memory Operations -- Basic Operations of the Stack -- Cortex-M3 Stack Implementation -- The Two-Stack Model in the Cortex-M3 -- Reset Sequence -- Chapter 4 - Instruction Sets -- Assembly Basics -- Assembler Language: Basic Syntax.

Assembler Language: Use of Suffixes -- Assembler Language: Unified Assembler Language -- Instruction List -- Unsupported Instructions -- Instruction Descriptions -- Assembler Language: Moving Data -- LDR and ADR Pseudo Instructions -- Assembler Language: Processing Data -- Assembler Language: Call and Unconditional Branch -- Assembler Language: Decisions and Conditional Branches -- Assembler Language: Combined Compare and Conditional Branch -- Assembler Language: Conditional Branches Using IT Instructions -- Assembler Language: Instruction Barrier and Memory Barrier Instructions -- Assembly Language: Saturation Operations -- Several Useful Instructions in the Cortex-M3 -- MSR and MRS -- IF-THEN -- CBZ and CBNZ -- SDIV and UDIV -- REV, REVH, and REVSH -- RBIT -- SXTB, SXTH, UXTB, and UXTH -- BFC and BFI -- UBFX and SBFX -- LDRD and STRD -- TBB and TBH -- Chapter 5 - Memory Systems -- Memory System Features Overview -- Memory Maps -- Memory Access Attributes -- Default Memory Access Permissions -- Bit-Band Operations -- Advantages of Bit-Band Operations -- Bit-Band Operation of Different Data Sizes -- Bit-Band Operations in C Programs -- Unaligned Transfers -- Exclusive Accesses -- Endian Mode -- Chapter 6 - Cortex-M3 Implementation Overview -- The Pipeline -- A Detailed Block Diagram -- Bus Interfaces on the Cortex-M3 -- The I-Code Bus -- The D-Code Bus -- The System Bus -- The External Private Peripheral Bus -- The Debug Access Port Bus -- Other Interfaces on the Cortex-M3 -- The External Private Peripheral Bus -- Typical Connections -- Reset Signals -- Chapter 7 - Exceptions -- Exception Types -- Definitions of Priority -- Vector Tables -- Interrupt Inputs and Pending Behavior -- Fault Exceptions -- Bus Faults -- Memory Management Faults -- Usage Faults -- Hard Faults -- Dealing with Faults -- SVC and PendSV.

Chapter 8 - The NVIC and Interrupt Control -- NVIC Overview -- The Basic Interrupt Configuration -- Interrupt Enable and Clear Enable -- Interrupt Pending and Clear Pending -- Priority Levels -- Active Status -- PRIMASK and FAULTMASK Special Registers -- The BASEPRI Special Register -- Configuration Registers for Other Exceptions -- Example Procedures of Setting Up an Interrupt -- Software Interrupts -- The SYSTICK Timer -- Chapter 9 - Interrupt Behavior -- Interrupt/Exception Sequences -- Stacking -- Vector Fetches -- Register Updates -- Exception Exits -- Nested Interrupts -- Tail-Chaining Interrupts -- Late Arrivals -- More on the Exception Return Value -- Interrupt Latency -- Faults Related to Interrupts -- Stacking -- Unstacking -- Vector Fetches -- Invalid Returns -- Chapter 10 - Cortex-M3 Programming -- Overview -- Using Assembly -- Using C -- The Interface Between Assembly and C -- A Typical Development Flow -- The First Step -- Producing Outputs -- The "Hello World" Example -- Using Data Memory -- Using Exclusive Access for Semaphores -- Using Bit-Band for Semaphores -- Working with Bit Field Extract and Table Branch -- Chapter 11 - Exceptions Programming -- Using Interrupts -- Stack setup -- Vector Table Setup -- Interrupt Priority Setup -- Enable the Interrupt -- Exception/Interrupt Handlers -- Software Interrupts -- Example with Exception Handlers -- Using SVC -- SVC Example: Use for Output Functions -- Using SVC with C -- Chapter 12 - Advanced Programming Features and System Behavior -- Running a System with Two Separate Stacks -- Double-Word Stack Alignment -- Nonbase Thread Enable -- Performance Considerations -- Lockup Situations -- What Happens During Lockup? -- Avoiding Lockup -- Chapter 13 - The Memory Protection Unit -- Overview -- MPU Registers -- Setting Up the MPU -- Typical Setup -- Example Use of the Subregion Disable.

Chapter 14 - Other Cortex-M3 Features -- The SYSTICK Timer -- Power Management -- Multiprocessor Communication -- Self-Reset Control -- Chapter 15 - Debug Architecture -- Debugging Features Overview -- CoreSight Overview -- Processor Debugging Interface -- The Debug Host Interface -- DP Module, AP Module, and DAP -- Trace Interface -- CoreSight Characteristics -- Debug Modes -- Debugging Events -- Breakpoint in the Cortex-M3 -- Accessing Register Content in Debug -- Other Core Debugging Features -- Chapter 16 - Debugging Components -- Introduction -- The Trace System in the Cortex-M3 -- Trace Components: Data Watchpoint and Trace -- Trace Components: Instrumentation Trace Macrocell -- Software Trace with the ITM -- Hardware Trace with ITM and DWT -- ITM Timestamp -- Trace Components: Embedded Trace Macrocell -- Trace Components: Trace Port Interface Unit -- The Flash Patch and Breakpoint Unit -- The AHB Access Port -- ROM Table -- Chapter 17 - Getting Started with Cortex-M3 Development -- Choosing a Cortex-M3 Product -- Differences Between Cortex-M3 Revision 0 and Revision 1 -- Revision 1 Change: Moving from JTAG-DP to SWJ-DP -- Development Tools -- C Compiler -- Embedded Operating System Support -- Chapter 18 - Porting Applications from the ARM7 to the Cortex-M3 -- Overview -- System Characteristics -- Memory Map -- Interrupts -- MPU -- System Control -- Operation Modes -- Assembly Language Files -- Thumb State -- ARM State -- C Program Files -- Precompiled Object Files -- Optimization -- Chapter 19 - Starting Cortex-M3 Development Using the GNU Tool Chain -- Background -- Getting the GNU Tool Chain -- Development Flow -- Examples -- Example 1: The First Program -- Example 2: Linking Multiple Files -- Example 3: A Simple "Hello World" Program -- Example 4: Data in RAM -- Example 5: C Only, Without Assembly File.

Example 6: C Only, with Standard C Startup Code -- Accessing Special Registers -- Using Unsupported Instructions -- Inline Assembler in the GNU C Compiler -- Chapter 20 - Getting Started with the KEIL RealView Microcontroller Development Kit -- Overview -- Getting Started with μVision -- Outputting the "Hello World" Message Via UART -- Testing the Software -- Using the Debugger -- The Instruction Set Simulator -- Modifying the Vector Table -- Stopwatch Example with Interrupts -- Appendix A - Cortex-M3 Instructions Summary -- Supported 16-Bit Thumb Instructions -- Supported 32-Bit Thumb-2 Instructions -- Appendix B - 16-Bit Thumb Instructions and Architecture Versions -- Appendix C - Cortex-M3 Exceptions Quick Reference -- Exception Types and Enables -- Stack Contents After Exception Stacking -- Appendix D - NVIC Registers Quick Reference -- Appendix E - Cortex-M3 Troubleshooting Guide -- Overview -- Developing Fault Handlers -- Report Fault Status Registers -- Report Stacked PC -- Read Fault Address Register -- Clear Fault Status Bits -- Others -- Understanding the Cause of the Fault -- Other Possible Problems -- Index -- A -- B -- C -- D -- E -- F -- H -- I -- L -- M -- N -- P -- Q -- R -- S -- T -- U -- V -- W -- X.

Capitalize on the power of the new ARM Cortex family in your embedded designs; this book shows you how!.

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Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2019. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.